Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers

Intel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers

Rezaur Rahman

Intel® Xeon Phi™ Coprocessor structure and instruments: The advisor for software builders presents builders a accomplished advent and in-depth examine the Intel Xeon Phi coprocessor structure and the corresponding parallel information constitution instruments and algorithms utilized in many of the technical computing functions for which it's appropriate. It additionally examines the resource code-level optimizations that may be played to take advantage of the strong positive aspects of the processor.

Xeon Phi is on the center of world’s quickest advertisement supercomputer, which because of the hugely parallel computing services of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark functionality in 2013. Extracting such stellar functionality in real-world functions calls for a cosmopolitan figuring out of the advanced interplay between parts, Xeon Phi cores, and the purposes operating on them.

In this ebook, Rezaur Rahman, an Intel chief within the improvement of the Xeon Phi coprocessor and the optimization of its purposes, provides and information all of the beneficial properties of Xeon Phi middle layout which are proper to the perform of software builders, similar to its vector devices, multithreading, cache hierarchy, and host-to-coprocessor conversation channels. development in this origin, he indicates builders how you can resolve real-world technical computing difficulties by means of identifying, deploying, and optimizing the on hand algorithms and knowledge constitution possible choices matching Xeon Phi’s features. From Rahman’s useful descriptions and wide code examples, the reader will achieve a operating wisdom of the Xeon Phi vector guideline set and the Xeon Phi microarchitecture wherein cores execute 512-bit guide streams in parallel.

What you’ll learn

How to calculate theoretical Gigaflops and bandwidth numbers at the and degree them via code segment
How to estimate latencies in fetching information from diversified cache hierarchies, together with reminiscence subsystems
How to degree PCIe bus bandwidth among the host and coprocessor
How to take advantage of energy administration and reliability gains equipped into the hardware
How to pick and control the simplest instruments to music specific Xeon Phi applications
Algorithms and knowledge constructions for optimizing Xeon Phi performance
Case reviews of real-world Xeon Phi technical computing purposes in molecular dynamics and monetary simulations
Who this ebook is for

This publication is for builders wishing to layout and improve technical computing functions to accomplish the top functionality to be had within the Intel Xeon Phi coprocessor undefined. It presents an effective base at the coprocessor structure, in addition to set of rules and knowledge constitution case experiences for Xeon Phi coprocessor. The booklet can also be of curiosity to scholars and practitioners in computing device engineering as a case examine for hugely parallel middle microarchitecture of contemporary day processors.

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